module async
(/*AUTOARG*/
   // Outputs
   inen, pop_dat, outen,
   // Inputs
   clk_a, xrst_a, clk_b, xrst_b, push, push_dat, pop
   );

    // public
    parameter          P_DW = 2; // data width

    input              clk_a               ; // I :
    input              xrst_a              ; // I :
    input              clk_b               ; // I :
    input              xrst_b              ; // I :
    input              push                ; // I :
    input   [P_DW-1:0] push_dat            ; // I :
    output             inen                ; // O :
    input              pop                 ; // I :
    output  [P_DW-1:0] pop_dat             ; // O :
    output             outen               ; // O :

    wire               w_dat_req0          ;
    wire               w_dat_req1          ;
    wire               w_dat_req2          ;
    wire               w_dat_req3          ;
    wire               w_dat_req4          ;
    wire               w_dat_req5          ;
    wire               w_dat_req6          ;
    wire               w_dat_req7          ;
    wire               w_dat_ack0          ;
    wire               w_dat_ack1          ;
    wire               w_dat_ack2          ;
    wire               w_dat_ack3          ;
    wire               w_dat_ack4          ;
    wire               w_dat_ack5          ;
    wire               w_dat_ack6          ;
    wire               w_dat_ack7          ;
    wire    [P_DW-1:0] w_dat0              ;
    wire    [P_DW-1:0] w_dat1              ;
    wire    [P_DW-1:0] w_dat2              ;
    wire    [P_DW-1:0] w_dat3              ;
    wire    [P_DW-1:0] w_dat4              ;
    wire    [P_DW-1:0] w_dat5              ;
    wire    [P_DW-1:0] w_dat6              ;
    wire    [P_DW-1:0] w_dat7              ;

    async_a #(P_DW) async_a
    (
        .clk      (clk_a               ), // I :
        .xrst     (xrst_a              ), // I :
        .push     (push                ), // I :
        .push_dat (push_dat            ), // I :
        .inen     (inen                ), // O :
        .dat_req0 (w_dat_req0          ), // O :
        .dat_req1 (w_dat_req1          ), // O :
        .dat_req2 (w_dat_req2          ), // O :
        .dat_req3 (w_dat_req3          ), // O :
        .dat_req4 (w_dat_req4          ), // O :
        .dat_req5 (w_dat_req5          ), // O :
        .dat_req6 (w_dat_req6          ), // O :
        .dat_req7 (w_dat_req7          ), // O :
        .dat_ack0 (w_dat_ack0          ), // I :
        .dat_ack1 (w_dat_ack1          ), // I :
        .dat_ack2 (w_dat_ack2          ), // I :
        .dat_ack3 (w_dat_ack3          ), // I :
        .dat_ack4 (w_dat_ack4          ), // I :
        .dat_ack5 (w_dat_ack5          ), // I :
        .dat_ack6 (w_dat_ack6          ), // I :
        .dat_ack7 (w_dat_ack7          ), // I :
        .dat0     (w_dat0              ), // O :
        .dat1     (w_dat1              ), // O :
        .dat2     (w_dat2              ), // O :
        .dat3     (w_dat3              ), // O :
        .dat4     (w_dat4              ), // O :
        .dat5     (w_dat5              ), // O :
        .dat6     (w_dat6              ), // O :
        .dat7     (w_dat7              )  // O :
    );

    async_b #(P_DW) async_b
    (
        .clk      (clk_b               ), // I :
        .xrst     (xrst_b              ), // I :
        .pop      (pop                 ), // I :
        .pop_dat  (pop_dat             ), // O :
        .outen    (outen               ), // O :
        .dat_req0 (w_dat_req0          ), // I :
        .dat_req1 (w_dat_req1          ), // I :
        .dat_req2 (w_dat_req2          ), // I :
        .dat_req3 (w_dat_req3          ), // I :
        .dat_req4 (w_dat_req4          ), // I :
        .dat_req5 (w_dat_req5          ), // I :
        .dat_req6 (w_dat_req6          ), // I :
        .dat_req7 (w_dat_req7          ), // I :
        .dat_ack0 (w_dat_ack0          ), // O :
        .dat_ack1 (w_dat_ack1          ), // O :
        .dat_ack2 (w_dat_ack2          ), // O :
        .dat_ack3 (w_dat_ack3          ), // O :
        .dat_ack4 (w_dat_ack4          ), // O :
        .dat_ack5 (w_dat_ack5          ), // O :
        .dat_ack6 (w_dat_ack6          ), // O :
        .dat_ack7 (w_dat_ack7          ), // O :
        .dat0     (w_dat0              ), // I :
        .dat1     (w_dat1              ), // I :
        .dat2     (w_dat2              ), // I :
        .dat3     (w_dat3              ), // I :
        .dat4     (w_dat4              ), // I :
        .dat5     (w_dat5              ), // I :
        .dat6     (w_dat6              ), // I :
        .dat7     (w_dat7              )  // I :
    );

endmodule

module async_a
(/*AUTOARG*/
   // Outputs
   inen, dat_req0, dat_req1, dat_req2, dat_req3, dat_req4, dat_req5,
   dat_req6, dat_req7, dat0, dat1, dat2, dat3, dat4, dat5, dat6, dat7,
   // Inputs
   clk, xrst, push, push_dat, dat_ack0, dat_ack1, dat_ack2, dat_ack3,
   dat_ack4, dat_ack5, dat_ack6, dat_ack7
   );

    // public
    parameter          P_DW    = 2; // data width

    // private
    parameter          P_DELAY = 1;
    parameter          P_PTR   = 3; // pointer size

    input              clk                 ; // I :
    input              xrst                ; // I :
    input              push                ; // I :
    input   [P_DW-1:0] push_dat            ; // I :
    output             inen                ; // O :
    output             dat_req0            ; // O :
    output             dat_req1            ; // O :
    output             dat_req2            ; // O :
    output             dat_req3            ; // O :
    output             dat_req4            ; // O :
    output             dat_req5            ; // O :
    output             dat_req6            ; // O :
    output             dat_req7            ; // O :
    input              dat_ack0            ; // I :
    input              dat_ack1            ; // I :
    input              dat_ack2            ; // I :
    input              dat_ack3            ; // I :
    input              dat_ack4            ; // I :
    input              dat_ack5            ; // I :
    input              dat_ack6            ; // I :
    input              dat_ack7            ; // I :
    output  [P_DW-1:0] dat0                ; // O :
    output  [P_DW-1:0] dat1                ; // O :
    output  [P_DW-1:0] dat2                ; // O :
    output  [P_DW-1:0] dat3                ; // O :
    output  [P_DW-1:0] dat4                ; // O :
    output  [P_DW-1:0] dat5                ; // O :
    output  [P_DW-1:0] dat6                ; // O :
    output  [P_DW-1:0] dat7                ; // O :

    reg     [P_PTR-1:0]   r_ptr                              ;
    reg     [7:0]         w_start                            ;
    reg                   w_inen                             ;
    wire    [7:0]         w_act                              ;
    wire                  w_dat_req0                         ;
    wire                  w_dat_req1                         ;
    wire                  w_dat_req2                         ;
    wire                  w_dat_req3                         ;
    wire                  w_dat_req4                         ;
    wire                  w_dat_req5                         ;
    wire                  w_dat_req6                         ;
    wire                  w_dat_req7                         ;
    reg     [P_DW-1:0]    r_dat0                             ;
    reg     [P_DW-1:0]    r_dat1                             ;
    reg     [P_DW-1:0]    r_dat2                             ;
    reg     [P_DW-1:0]    r_dat3                             ;
    reg     [P_DW-1:0]    r_dat4                             ;
    reg     [P_DW-1:0]    r_dat5                             ;
    reg     [P_DW-1:0]    r_dat6                             ;
    reg     [P_DW-1:0]    r_dat7                             ;

    assign inen     = w_inen;
    assign dat_req0 = w_dat_req0;
    assign dat_req1 = w_dat_req1;
    assign dat_req2 = w_dat_req2;
    assign dat_req3 = w_dat_req3;
    assign dat_req4 = w_dat_req4;
    assign dat_req5 = w_dat_req5;
    assign dat_req6 = w_dat_req6;
    assign dat_req7 = w_dat_req7;
    assign dat0     = r_dat0;
    assign dat1     = r_dat1;
    assign dat2     = r_dat2;
    assign dat3     = r_dat3;
    assign dat4     = r_dat4;
    assign dat5     = r_dat5;
    assign dat6     = r_dat6;
    assign dat7     = r_dat7;

    //
    // Write pointer control
    //

    // r_ptr[P_PTR-1:0]
    always @(posedge clk or negedge xrst) begin
        if (!xrst) begin
            r_ptr <= #P_DELAY {P_PTR{1'b0}};
        end else if (push == 1'b1) begin
            r_ptr <= #P_DELAY r_ptr + {{(P_PTR-1){1'b0}},1'b1};
        end
    end

    // w_start[7:0]
    always @(/*AS*/push or r_ptr) begin
        case (r_ptr)
            3'd0: if (push == 1'b1) begin w_start = 8'b00000001; end else begin w_start = 8'b00000000; end
            3'd1: if (push == 1'b1) begin w_start = 8'b00000010; end else begin w_start = 8'b00000000; end
            3'd2: if (push == 1'b1) begin w_start = 8'b00000100; end else begin w_start = 8'b00000000; end
            3'd3: if (push == 1'b1) begin w_start = 8'b00001000; end else begin w_start = 8'b00000000; end
            3'd4: if (push == 1'b1) begin w_start = 8'b00010000; end else begin w_start = 8'b00000000; end
            3'd5: if (push == 1'b1) begin w_start = 8'b00100000; end else begin w_start = 8'b00000000; end
            3'd6: if (push == 1'b1) begin w_start = 8'b01000000; end else begin w_start = 8'b00000000; end
            3'd7: if (push == 1'b1) begin w_start = 8'b10000000; end else begin w_start = 8'b00000000; end
            default : w_start = 8'b00000000;
        endcase
    end

    // w_inen
    always @(/*AS*/r_ptr or w_act) begin
        case (r_ptr)
            3'd0: if (w_act[0] == 1'b0) begin w_inen = 1'b1; end else begin w_inen = 1'b0; end
            3'd1: if (w_act[1] == 1'b0) begin w_inen = 1'b1; end else begin w_inen = 1'b0; end
            3'd2: if (w_act[2] == 1'b0) begin w_inen = 1'b1; end else begin w_inen = 1'b0; end
            3'd3: if (w_act[3] == 1'b0) begin w_inen = 1'b1; end else begin w_inen = 1'b0; end
            3'd4: if (w_act[4] == 1'b0) begin w_inen = 1'b1; end else begin w_inen = 1'b0; end
            3'd5: if (w_act[5] == 1'b0) begin w_inen = 1'b1; end else begin w_inen = 1'b0; end
            3'd6: if (w_act[6] == 1'b0) begin w_inen = 1'b1; end else begin w_inen = 1'b0; end
            3'd7: if (w_act[7] == 1'b0) begin w_inen = 1'b1; end else begin w_inen = 1'b0; end
            default : w_inen = 1'b0;
        endcase
    end

    // w_act[7:0]
    // w_dat_req0
    // w_dat_req1
    // w_dat_req2
    // w_dat_req3
    // w_dat_req4
    // w_dat_req5
    // w_dat_req6
    // w_dat_req7
    handmst handmst_0(.clk(clk),.xrst(xrst),.start(w_start[0]),.act(w_act[0]),.finish(/* open */),.req(w_dat_req0),.ack(dat_ack0));
    handmst handmst_1(.clk(clk),.xrst(xrst),.start(w_start[1]),.act(w_act[1]),.finish(/* open */),.req(w_dat_req1),.ack(dat_ack1));
    handmst handmst_2(.clk(clk),.xrst(xrst),.start(w_start[2]),.act(w_act[2]),.finish(/* open */),.req(w_dat_req2),.ack(dat_ack2));
    handmst handmst_3(.clk(clk),.xrst(xrst),.start(w_start[3]),.act(w_act[3]),.finish(/* open */),.req(w_dat_req3),.ack(dat_ack3));
    handmst handmst_4(.clk(clk),.xrst(xrst),.start(w_start[4]),.act(w_act[4]),.finish(/* open */),.req(w_dat_req4),.ack(dat_ack4));
    handmst handmst_5(.clk(clk),.xrst(xrst),.start(w_start[5]),.act(w_act[5]),.finish(/* open */),.req(w_dat_req5),.ack(dat_ack5));
    handmst handmst_6(.clk(clk),.xrst(xrst),.start(w_start[6]),.act(w_act[6]),.finish(/* open */),.req(w_dat_req6),.ack(dat_ack6));
    handmst handmst_7(.clk(clk),.xrst(xrst),.start(w_start[7]),.act(w_act[7]),.finish(/* open */),.req(w_dat_req7),.ack(dat_ack7));

    //
    // Write data latch
    //

    // r_dat0[P_DW-1:0]
    always @(posedge clk or negedge xrst) begin
        if (!xrst) begin
            r_dat0 <= #P_DELAY {P_DW{1'b0}};
        end else if (push == 1'b1 && r_ptr == 3'd0) begin
            r_dat0 <= #P_DELAY push_dat;
        end
    end

    // r_dat1[P_DW-1:0]
    always @(posedge clk or negedge xrst) begin
        if (!xrst) begin
            r_dat1 <= #P_DELAY {P_DW{1'b0}};
        end else if (push == 1'b1 && r_ptr == 3'd1) begin
            r_dat1 <= #P_DELAY push_dat;
        end
    end

    // r_dat2[P_DW-1:0]
    always @(posedge clk or negedge xrst) begin
        if (!xrst) begin
            r_dat2 <= #P_DELAY {P_DW{1'b0}};
        end else if (push == 1'b1 && r_ptr == 3'd2) begin
            r_dat2 <= #P_DELAY push_dat;
        end
    end

    // r_dat3[P_DW-1:0]
    always @(posedge clk or negedge xrst) begin
        if (!xrst) begin
            r_dat3 <= #P_DELAY {P_DW{1'b0}};
        end else if (push == 1'b1 && r_ptr == 3'd3) begin
            r_dat3 <= #P_DELAY push_dat;
        end
    end

    // r_dat4[P_DW-1:0]
    always @(posedge clk or negedge xrst) begin
        if (!xrst) begin
            r_dat4 <= #P_DELAY {P_DW{1'b0}};
        end else if (push == 1'b1 && r_ptr == 3'd4) begin
            r_dat4 <= #P_DELAY push_dat;
        end
    end

    // r_dat5[P_DW-1:0]
    always @(posedge clk or negedge xrst) begin
        if (!xrst) begin
            r_dat5 <= #P_DELAY {P_DW{1'b0}};
        end else if (push == 1'b1 && r_ptr == 3'd5) begin
            r_dat5 <= #P_DELAY push_dat;
        end
    end

    // r_dat6[P_DW-1:0]
    always @(posedge clk or negedge xrst) begin
        if (!xrst) begin
            r_dat6 <= #P_DELAY {P_DW{1'b0}};
        end else if (push == 1'b1 && r_ptr == 3'd6) begin
            r_dat6 <= #P_DELAY push_dat;
        end
    end

    // r_dat7[P_DW-1:0]
    always @(posedge clk or negedge xrst) begin
        if (!xrst) begin
            r_dat7 <= #P_DELAY {P_DW{1'b0}};
        end else if (push == 1'b1 && r_ptr == 3'd7) begin
            r_dat7 <= #P_DELAY push_dat;
        end
    end

endmodule

module async_b
(/*AUTOARG*/
   // Outputs
   pop_dat, outen, dat_ack0, dat_ack1, dat_ack2, dat_ack3, dat_ack4,
   dat_ack5, dat_ack6, dat_ack7,
   // Inputs
   clk, xrst, pop, dat_req0, dat_req1, dat_req2, dat_req3, dat_req4,
   dat_req5, dat_req6, dat_req7, dat0, dat1, dat2, dat3, dat4, dat5,
   dat6, dat7
   );

    // public
    parameter          P_DW    = 2; // data width

    // private
    parameter          P_DELAY = 1;
    parameter          P_PTR   = 3; // pointer size

    input              clk                 ; // I :
    input              xrst                ; // I :
    input              pop                 ; // I :
    output  [P_DW-1:0] pop_dat             ; // O :
    output             outen               ; // O :
    input              dat_req0            ; // I :
    input              dat_req1            ; // I :
    input              dat_req2            ; // I :
    input              dat_req3            ; // I :
    input              dat_req4            ; // I :
    input              dat_req5            ; // I :
    input              dat_req6            ; // I :
    input              dat_req7            ; // I :
    output             dat_ack0            ; // O :
    output             dat_ack1            ; // O :
    output             dat_ack2            ; // O :
    output             dat_ack3            ; // O :
    output             dat_ack4            ; // O :
    output             dat_ack5            ; // O :
    output             dat_ack6            ; // O :
    output             dat_ack7            ; // O :
    input   [P_DW-1:0] dat0                ; // I :
    input   [P_DW-1:0] dat1                ; // I :
    input   [P_DW-1:0] dat2                ; // I :
    input   [P_DW-1:0] dat3                ; // I :
    input   [P_DW-1:0] dat4                ; // I :
    input   [P_DW-1:0] dat5                ; // I :
    input   [P_DW-1:0] dat6                ; // I :
    input   [P_DW-1:0] dat7                ; // I :

    reg     [P_PTR-1:0]   w_ptr                              ;
    reg     [P_PTR-1:0]   r_ptr                              ;
    reg     [7:0]         w_finish                           ;
    reg                   w_outen                            ;
    wire    [7:0]         w_act                              ;
    wire                  w_dat_ack0                         ;
    wire                  w_dat_ack1                         ;
    wire                  w_dat_ack2                         ;
    wire                  w_dat_ack3                         ;
    wire                  w_dat_ack4                         ;
    wire                  w_dat_ack5                         ;
    wire                  w_dat_ack6                         ;
    wire                  w_dat_ack7                         ;
    reg     [P_DW-1:0]    r_dat                              ;

    assign pop_dat  = r_dat;
    assign outen    = w_outen;
    assign dat_ack0 = w_dat_ack0;
    assign dat_ack1 = w_dat_ack1;
    assign dat_ack2 = w_dat_ack2;
    assign dat_ack3 = w_dat_ack3;
    assign dat_ack4 = w_dat_ack4;
    assign dat_ack5 = w_dat_ack5;
    assign dat_ack6 = w_dat_ack6;
    assign dat_ack7 = w_dat_ack7;

    //
    // Read pointer control
    //

    // w_ptr[P_PTR-1:0]
    always @(/*AS*/pop or r_ptr) begin
        if (pop == 1'b1) begin
            w_ptr = r_ptr + {{(P_PTR-1){1'b0}},1'b1};
        end else begin
            w_ptr = r_ptr;
        end
    end

    // r_ptr[P_PTR-1:0]
    always @(posedge clk or negedge xrst) begin
        if (!xrst) begin
            r_ptr <= #P_DELAY {P_PTR{1'b0}};
        end else begin
            r_ptr <= #P_DELAY w_ptr;
        end
    end

    // w_finish[7:0]
    always @(/*AS*/pop or r_ptr) begin
        case (r_ptr)
            3'd0: if (pop == 1'b1) begin w_finish = 8'b00000001; end else begin w_finish = 8'b00000000; end
            3'd1: if (pop == 1'b1) begin w_finish = 8'b00000010; end else begin w_finish = 8'b00000000; end
            3'd2: if (pop == 1'b1) begin w_finish = 8'b00000100; end else begin w_finish = 8'b00000000; end
            3'd3: if (pop == 1'b1) begin w_finish = 8'b00001000; end else begin w_finish = 8'b00000000; end
            3'd4: if (pop == 1'b1) begin w_finish = 8'b00010000; end else begin w_finish = 8'b00000000; end
            3'd5: if (pop == 1'b1) begin w_finish = 8'b00100000; end else begin w_finish = 8'b00000000; end
            3'd6: if (pop == 1'b1) begin w_finish = 8'b01000000; end else begin w_finish = 8'b00000000; end
            3'd7: if (pop == 1'b1) begin w_finish = 8'b10000000; end else begin w_finish = 8'b00000000; end
            default : w_finish = 8'b00000000;
        endcase
    end

    // w_outen
    always @(/*AS*/r_ptr or w_act) begin
        case (r_ptr)
            3'd0: if (w_act[0] == 1'b1) begin w_outen = 1'b1; end else begin w_outen = 1'b0; end
            3'd1: if (w_act[1] == 1'b1) begin w_outen = 1'b1; end else begin w_outen = 1'b0; end
            3'd2: if (w_act[2] == 1'b1) begin w_outen = 1'b1; end else begin w_outen = 1'b0; end
            3'd3: if (w_act[3] == 1'b1) begin w_outen = 1'b1; end else begin w_outen = 1'b0; end
            3'd4: if (w_act[4] == 1'b1) begin w_outen = 1'b1; end else begin w_outen = 1'b0; end
            3'd5: if (w_act[5] == 1'b1) begin w_outen = 1'b1; end else begin w_outen = 1'b0; end
            3'd6: if (w_act[6] == 1'b1) begin w_outen = 1'b1; end else begin w_outen = 1'b0; end
            3'd7: if (w_act[7] == 1'b1) begin w_outen = 1'b1; end else begin w_outen = 1'b0; end
            default : w_outen = 1'b0;
        endcase
    end

    // w_act[7:0]
    // w_dat_ack0
    // w_dat_ack1
    // w_dat_ack2
    // w_dat_ack3
    // w_dat_ack4
    // w_dat_ack5
    // w_dat_ack6
    // w_dat_ack7
    handslv handslv_0 (.clk(clk),.xrst(xrst),.start(/* open */),.act(w_act[0]),.finish(w_finish[0]),.req(dat_req0),.ack(w_dat_ack0));
    handslv handslv_1 (.clk(clk),.xrst(xrst),.start(/* open */),.act(w_act[1]),.finish(w_finish[1]),.req(dat_req1),.ack(w_dat_ack1));
    handslv handslv_2 (.clk(clk),.xrst(xrst),.start(/* open */),.act(w_act[2]),.finish(w_finish[2]),.req(dat_req2),.ack(w_dat_ack2));
    handslv handslv_3 (.clk(clk),.xrst(xrst),.start(/* open */),.act(w_act[3]),.finish(w_finish[3]),.req(dat_req3),.ack(w_dat_ack3));
    handslv handslv_4 (.clk(clk),.xrst(xrst),.start(/* open */),.act(w_act[4]),.finish(w_finish[4]),.req(dat_req4),.ack(w_dat_ack4));
    handslv handslv_5 (.clk(clk),.xrst(xrst),.start(/* open */),.act(w_act[5]),.finish(w_finish[5]),.req(dat_req5),.ack(w_dat_ack5));
    handslv handslv_6 (.clk(clk),.xrst(xrst),.start(/* open */),.act(w_act[6]),.finish(w_finish[6]),.req(dat_req6),.ack(w_dat_ack6));
    handslv handslv_7 (.clk(clk),.xrst(xrst),.start(/* open */),.act(w_act[7]),.finish(w_finish[7]),.req(dat_req7),.ack(w_dat_ack7));

    //
    // Read data latch
    //

    // r_dat[P_DW-1:0]
    always @(posedge clk or negedge xrst) begin
        if (!xrst) begin
            r_dat <= #P_DELAY {P_DW{1'b0}};
        end else begin
            case (w_ptr)
                3'd0:    r_dat <= #P_DELAY dat0;
                3'd1:    r_dat <= #P_DELAY dat1;
                3'd2:    r_dat <= #P_DELAY dat2;
                3'd3:    r_dat <= #P_DELAY dat3;
                3'd4:    r_dat <= #P_DELAY dat4;
                3'd5:    r_dat <= #P_DELAY dat5;
                3'd6:    r_dat <= #P_DELAY dat6;
                3'd7:    r_dat <= #P_DELAY dat7;
                default: r_dat <= #P_DELAY r_dat;
            endcase
        end
    end

endmodule