module handslv2
(/*AUTOARG*/
   // Outputs
   start, act, ack,
   // Inputs
   clk, xrst, finish, req, enable
   );

    // public
    // private
    parameter      P_DELAY     = 1;

    parameter      P_INIT      = 2'd0;
    parameter      P_ACK       = 2'd1;
    parameter      P_ENB       = 2'd2;
    parameter      P_WAIT      = 2'd3;

    input    clk                 ; // I :
    input    xrst                ; // I :
    output   start               ; // O :
    output   act                 ; // O :
    input    finish              ; // I :
    input    req                 ; // I :
    output   ack                 ; // O :
    input    enable              ; // I :

    reg     [1:0]         w_state                            ;
    reg     [1:0]         r_state                            ;
    reg                   r_req0                             ;
    reg                   r_req1                             ;
    reg                   r_enable0                          ;
    reg                   r_enable1                          ;
    reg                   r_ack                              ;
    reg                   r_start                            ;
    wire                  w_act                              ;

    assign start = r_start;
    assign act   = w_act;
    assign ack   = r_ack;

    // w_state[1:0]
    always @(/*AS*/finish or r_enable1 or r_req1 or r_state) begin
        case (r_state)
            P_INIT:
                if (r_req1 == 1'b1) begin
                    w_state = P_ACK;
                end else begin
                    w_state = r_state;
                end
            P_ACK:
                if (r_req1 == 1'b0) begin
                    w_state = P_ENB;
                end else begin
                    w_state = r_state;
                end
            P_ENB:
                if (r_enable1 == 1'b0) begin
                    w_state = P_WAIT;
                end else begin
                    w_state = r_state;
                end
            P_WAIT:
                if (finish == 1'b1) begin
                    w_state = P_INIT;
                end else begin
                    w_state = r_state;
                end
            default:
                w_state = P_INIT;
        endcase
    end

    // r_state[1:0]
    always @(posedge clk or negedge xrst) begin
        if (!xrst) begin
            r_state <= #P_DELAY P_INIT;
        end else begin
            r_state <= #P_DELAY w_state;
        end
    end

    // r_req0
    // r_req1
    always @(posedge clk or negedge xrst) begin
        if (!xrst) begin
            r_req0 <= #P_DELAY 1'b0;
            r_req1 <= #P_DELAY 1'b0;
        end else begin
            r_req0 <= #P_DELAY req;
            r_req1 <= #P_DELAY r_req0;
        end
    end

    // r_enable0
    // r_enable1
    always @(posedge clk or negedge xrst) begin
        if (!xrst) begin
            r_enable0 <= #P_DELAY 1'b0;
            r_enable1 <= #P_DELAY 1'b0;
        end else begin
            r_enable0 <= #P_DELAY enable;
            r_enable1 <= #P_DELAY r_enable0;
        end
    end

    // r_ack
    always @(posedge clk or negedge xrst) begin
        if (!xrst) begin
            r_ack <= #P_DELAY 1'b0;
        end else if (r_state == P_INIT && w_state == P_ACK) begin
            r_ack <= #P_DELAY 1'b1;
        end else if (r_state == P_ACK && w_state == P_ENB) begin
            r_ack <= #P_DELAY 1'b0;
        end
    end

    // r_start
    always @(posedge clk or negedge xrst) begin
        if (!xrst) begin
            r_start <= #P_DELAY 1'b0;
        end else if (r_state == P_ENB && w_state == P_WAIT) begin
            r_start <= #P_DELAY 1'b1;
        end else begin
            r_start <= #P_DELAY 1'b0;
        end
    end

    // w_act
    assign w_act = (r_state == P_WAIT);

endmodule